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| 74AC646 * 74ACT646 Octal Transceiver/Register with 3-STATE Outputs November 1988 Revised December 1998 74AC646 * 74ACT646 Octal Transceiver/Register with 3-STATE Outputs General Description The AC/ACT646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4. Features s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil dual-in-line package s Outputs source/sink 24 mA s ACT646 has TTL compatible inputs Ordering Code: Order Number 74AC646SC 74AC646SPC 74ACT646SPC Package Number M24B N24C N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbols Connection Diagram Pin Assignment for DIP and SOIC IEEE/IEC Pin Descriptions Pin Names A0-A7 B0-B7 CPAB, CPBA SAB, SBA G DIR FACTTM is a trademark of Fairchild Semiconductor Corporation. Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input (c) 1999 Fairchild Semiconductor Corporation DS010132.prf www.fairchildsemi.com 74AC646 * 74ACT646 Function Table Inputs G H H H L L L L L L L L DIR X X X H H H H L L L L CPAB CPBA SAB H or L SBA X X X X X X X L L H H Output Input Input Output Input Input Data I/O (Note 1) A0-A7 B0-B7 Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn--Real Time (Transparent Mode) Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An --Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An Function X H or L H or L X X X L L H H X X X X X X X X X X X X X X H or L X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Real Time Transfer A-Bus to B-Bus Storage from Bus to Register FIGURE 1. FIGURE 3. Real Time Transfer B-Bus to A-Bus Transfer from Register to Bus FIGURE 4. FIGURE 2. www.fairchildsemi.com 2 74AC646 * 74ACT646 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74AC646 * 74ACT646 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V Recommended Operating Conditions Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications. 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD ICC (Note 5) IOZT Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 0.6 6.0 A 5.5 5.5 5.5 5.5 8.0 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 75 -75 80.0 A mA mA A V IOH = 12 mA IOL = 24 mA IOH = 24 mA (Note 3) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Units Conditions VOUT = 0.1V V or VCC - 0.1V VOUT = 0.1V V or VCC - 0.1V IOUT = -50 A V IOH = -12 mA V IOH = -24 mA IOH = -24 mA (Note 3) IOUT = 50 A V www.fairchildsemi.com 4 74AC646 * 74ACT646 DC Electrical Characteristics for ACT Symbol Parameter VCC (V) VIH VIL VOH Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 Maximum Input Leakage Current Maximum ICC/Input IOLD IOHD ICC IOZT Minimum Dynamic Output Current (Note 7) Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 0.6 6.0 A 5.5 5.5 5.5 5.5 5.5 8.0 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 VIN = VIL or VIH 3.76 4.76 0.1 0.1 VIN = VIL or VIH 0.44 0.44 1.0 1.5 75 -75 80.0 A mA mA mA A V IOL= 24 mA IOL = 24 mA (Note 6) VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time. Units Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A V V V V V IOH= -24 mA IOH= -24 mA (Note 6) IOUT = 50 A AC Electrical Characteristics for AC VCC Symbol Parameter (V) (Note 8) tPLH Propagation Delay Clock to Bus tPHL Propagation Delay Clock to Bus tPLH Propagation Delay Bus to Bus tPHL Propagation Delay Bus to Bus tPLH Propagation Delay SBA or SAB to An or Bn (w/ An or Bn HIGH or LOW) tPHL Propagation Delay SBA or SAB to An or Bn (w/ An or Bn HIGH or LOW) tPZH Enable Time G to An or Bn 3.3 5.0 2.5 1.5 7.0 5.0 11.5 8.5 2.0 1.5 12.5 9.0 ns 3.3 5.0 1.5 1.5 8.5 6.0 13.5 10.0 1.5 1.5 15.0 11.0 ns 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min 4.0 2.5 3.0 2.0 2.5 1.5 1.5 1.5 2.0 1.5 TA = +25C CL = 50 pF Typ 10.5 7.5 9.5 6.5 7.5 5.0 7.5 5.0 8.5 6.0 Max 16.5 12.0 14.5 10.5 12.0 8.0 12.5 9.0 13.5 10.0 TA = -40C to +85C CL = 50 pF Min 3.0 2.0 2.5 1.5 2.0 1.0 1.5 1.0 1.5 1.5 Max 18.5 13.0 16.0 11.5 13.5 9.0 13.5 9.5 15.5 11.0 ns ns ns ns ns Units 5 www.fairchildsemi.com 74AC646 * 74ACT646 AC Electrical Characteristics for AC VCC Symbol Parameter (V) (Note 8) tPZL Enable Time G to An or Bn tPHZ Disable Time G to An or Bn tPLZ Disable Time G to An or Bn tPZH Enable Time DIR to An or Bn tPZL Enable Time DIR to An or Bn tPHZ Disable Time DIR to An or Bn tPLZ Disable Time DIR to An or Bn Note 8: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V (Continued) TA = +25C CL = 50 pF Min 2.5 1.5 3.0 2.0 2.0 1.5 2.0 1.5 2.5 1.5 2.5 1.5 1.5 1.5 Typ 7.5 5.5 8.0 6.5 7.5 6.0 6.5 5.0 7.0 5.0 7.5 5.5 7.5 5.5 Max 12.5 9.0 12.5 10.0 12.0 9.5 11.0 7.5 11.5 8.0 11.5 9.5 12.0 9.5 TA = -40C to +85C CL = 50 pF Min 2.0 1.5 2.5 2.0 2.0 1.5 1.5 1.0 2.0 1.0 1.5 1.5 1.5 1.5 Max 14.0 10.0 13.5 11.0 13.5 10.5 12.0 8.5 13.0 9.0 12.5 10.0 13.5 10.5 ns ns ns ns ns ns ns Units 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 AC Operating Requirements for AC VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW Note 9: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V TA = +25C CL = 50 pF Typ 2.0 1.5 -1.5 -0.5 2.0 2.0 5.0 4.0 0 0.5 3.5 3.5 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 5.5 4.5 0 1.0 4.5 3.5 ns ns ns Units (V) (Note 9) 3.3 5.0 3.3 5.0 3.3 5.0 www.fairchildsemi.com 6 74AC646 * 74ACT646 AC Electrical Characteristics for ACT VCC Symbol Parameter (V) (Note 10) tPLH Propagation Delay Clock to Bus tPHL Propagation Delay Clock to Bus tPLH Propagation Delay Bus to Bus tPHL Propagation Delay Bus to Bus tPLH Propagation Delay SBA or SAB to An to Bn (w/An or Bn HIGH or LOW) tPHL Propagation Delay SBA or SAB to An to Bn (w/An or Bn HIGH or LOW) tPZH Enable Time G to An or Bn tPZL Enable Time G to An or Bn tPHZ Disable Time G to An or Bn tPLZ Disable Time G to An or Bn tPZH Enable Time DIR to An or Bn tPZL Enable Time DIR to An or Bn tPHZ Disable Time DIR to An or Bn tPLZ Disable Time DIR to An or Bn Note 10: Voltage Range 5.0 is 5.0V 0.5V TA = +25C CL = 50 pF Min 3.5 Typ 12.0 Max 14.5 TA = -40C to +85C CL = 50 pF Min 3.0 Max 16.0 ns Units 5.0 5.0 4.0 12.0 14.5 3.5 16.0 ns 5.0 3.0 8.5 10.5 2.5 11.5 ns 5.0 2.5 8.5 10.5 2.0 11.5 ns 5.0 3.0 9.5 11.5 2.5 12.5 ns 5.0 3.0 9.5 11.5 2.5 12.5 ns 5.0 2.0 9.0 11.0 1.5 12.0 ns 5.0 3.5 9.0 11.0 3.0 12.0 ns 5.0 5.0 10.5 13.0 4.5 14.5 ns 5.0 3.5 10.0 12.5 3.0 14.0 ns 5.0 2.0 6.5 10.5 1.5 11.5 ns 5.0 3.5 6.5 10.5 3.0 11.5 ns 5.0 5.0 8.5 12.5 4.5 13.5 ns 5.0 3.5 8.5 12.5 3.0 13.5 ns 7 www.fairchildsemi.com 74AC646 * 74ACT646 AC Operating Requirements for ACT VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW BUS to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW Note 11: Voltage Range 5.0 is 5.0V 0.5V TA = +25C CL = 50 pF Typ 2.5 0 4.5 7.0 2.5 7.0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 8.0 2.5 8.0 ns ns ns Units (V) (Note 11) 5.0 5.0 5.0 Capacitance Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Typ 4.5 15.0 60.0 Units pF pF pF VCC = OPEN VCC = 5.0V VCC = 5.0V Conditions www.fairchildsemi.com 8 74AC646 * 74ACT646 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M24B 9 www.fairchildsemi.com 74AC646 * 74ACT646 Octal Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300" Wide Package Number N24C LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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